Author: steve-myers
Posted: Wed Sep 07, 2016 9:19 am (GMT 5.5)
No, it doesn't work that way. There are two issues.
Posted: Wed Sep 07, 2016 9:19 am (GMT 5.5)
No, it doesn't work that way. There are two issues.
- Going back to my raw TOD clock, those 3 low order hexadecimal 0s represent bits 52 through 63. In other words, they represent a precision of less than 1 micro second.
- Now, the -value I formatted is from the CVDG; in terms of ordinary math, -D... is a 2's complement negative number, CVDG produced a negative packed decimal number. Now I suppose I could change the D to a C in the packed decimal number, or change the D... to microseconds before the CVDG with
LM evenreg,oddreg,CLOCKVAL
SRDL evenreg,12
STM evenreg,oddreg,CLOCKVAL
LG reg,CLOCKVAL
CVDG reg,QUADWORD
which would give me 000D... to convert and a positive number in microseconds. But then you have lost the fraction of microseconds. Back in the days when I used a real z machine rather than Hercules, all 12 of those fraction of a microsecond bits were used!
Yes, there is an SRLG instruction, but a quick read of Principles of Operation leaves me confused as you specify 2 registers and they interact in some way I'm not sure I understand without some experimentation I can't do quickly enough for this post.